Describe behavior
Bring a Workcraft STG .g, a circuit .work, or ACT CHP. Start from intent, not a preselected pipeline.
Early access · asynchronous digital design
Design the event, not the clock.
AsyncSilica is an AI-assisted workspace for exploring asynchronous hardware — from handshake intent and CHP through verified STGs, mapped Verilog, and physical layout previews.
An independent project by Prithvi Deyannavar · a research prototype for engineers and researchers building beyond synchronous assumptions.
WORKCRAFT / RUN 0042 exploring
STG verifiedNET mappedPDK sky130l
STG verification·CHP synthesis·structural Verilog·layout preview·STG verification·CHP synthesis
One thread of intent
From handshake to
physical intuition.
Keep the reasoning visible as a design moves through the asynchronous toolchain. Ask for one operation at a time; inspect the artifacts it produces.
Verify & synthesize
Workcraft handles STG verification and synthesis. ACT handles CHP synthesis, simulation, and the act2v / v2act bridge.
formal · functional · mappedExplore the physical
Follow ACT components through placement and routing, Magic GDSII, Netgen LVS, and KLayout previews.
sky130 · GDSII · LVSChoose your route
A toolchain you can
read as you go.
Explore the documented paths independently. AsyncSilica does not silently choose a route or chain operations without an explicit request.
ACT NATIVE PATH
Describe channels. Simulate the handshake.
Use ACT tools for CHP synthesis and functional simulation, then export or bridge when the design needs to meet another representation.
CHP .actsynth2 netlistact2v Verilog
WORKCRAFT PATH
Verify transitions. Synthesize structure.
Use Workcraft for STG verification and synthesis, including technology mapping for structural Verilog that can cross into the ACT ecosystem.
STG .gMPSat verifyVerilog mapped
PHYSICAL EXPLORATION
Follow a structural netlist toward layout.
Explore the ACT physical path with SKY130 / sky130l, placement and routing components, Magic GDSII, Netgen LVS, and KLayout previews.
RTL structuralactflow place / routeGDSII Magic
Built for the in-between
Technical depth,
without the black box.
AsyncSilica helps make asynchronous design work legible: the model, the tool call, and the generated artifact stay close together.
Tell us what you are building ↗01
Agent-guided, not agent-decided
Explicit requests drive each operation. No hidden default workflow or automatic synthesis chain.
02
Real artifacts at every step
Inspect timing diagrams, STGs, mapped Verilog, ACT, GDSII, and reports as they are generated.
03
A bridge for experiments
Structural technology-mapped Verilog is the hand-off between Workcraft synthesis and ACT's native flow.
Research-guided exploration
Explore design
alternatives with care.
AsyncSilica helps compare and carry forward design alternatives through opt-in, evidence-led workflows—not a fully autonomous multi-agent system.
01CHP / STG alternativesResearch-mode variant generation
Sampling-temperature variation generates CHP/STG candidates for generate_and_validate_stg. Each variant goes through the existing self-verifying flow, and the winner is selected by verified structural size.
Structural hints are planned for a future Stage 2; they are not built yet.
02Persistent research memoryOpt-in Archive across local sessions
Adapted to one local Llama model, the workflow can append results to a persistent Archive across sessions. Archive Reviewer notes cover archived results, including non-winning variants, so useful context is not lost after one run.
This is not a literal multi-frontier-agent Station replica.
03On-request reflectionExplicit tools for reusable lessons
archive_and_review_result and run_meta_reflection_now make archival and Meta-Reflection explicit. Archive paths are re-verified before archival, and reflection synthesizes reusable lessons from prior results.
The workflow is opt-in/manual rather than automatic. There is no dashboard Archive browser yet; Archive data is currently kept as JSONL/Markdown on disk.
Inputs / outputs
Bring the design
you already have.
INPUT
STG & circuit models
.g · .work · timing diagramsINPUT
ACT / CHP programs
.act · simulation traces · channel modelsOUTPUT
Design artifactsstructural Verilog · ACT · GDSII · LVS reports · previews
Physical path
Open tooling.
Concrete targets.
The current physical exploration path is built around the open SKY130 ecosystem, with a design that can grow toward additional PDKs over time.
130nm
SKY130 / sky130l
Currently supported for physical exploration
More PDKs · planned extensibilityGood questions
Start with the
honest version.
Is AsyncSilica production-ready?
No. This is an active research prototype. It is useful for exploring flows and artifacts, but it does not promise autonomous signoff, guaranteed silicon, or production readiness.
Does the agent choose a toolchain for me?
No. AsyncSilica follows the operation you ask for. If a request is ambiguous between Workcraft and ACT routes, the agent should ask you to choose.
What PDKs can I use?
SKY130 / sky130l is the current supported physical target. Additional PDK support is planned as the interfaces mature; unsupported PDKs should not be assumed to work.
Who is early access for?
Researchers, hardware engineers, students, and curious builders working with asynchronous digital design are all welcome. Tell us what you want to explore.
Make the next run count
Help shape the
design workspace.
Leave a note and we will follow up when the next private preview is ready.